Field-effect transistors from lithographically patterned cadmium selenide nanowire arrays.

Field-effect transistors (NWFETs) have been prepared from arrays of polycrystalline cadmium selenide (pc-CdSe) nanowires using a back gate configuration. pc-CdSe nanowires were fabricated using the lithographically patterned nanowire electrodeposition (LPNE) process on SiO(2)/Si substrates. After electrodeposition, pc-CdSe nanowires were thermally annealed at 300 °C × 4 h either with or without exposure to CdCl(2) in methanol-a grain growth promoter. The influence of CdCl(2) treatment was to increase the mean grain diameter from 10 to 80 nm as determined by grazing incidence X-ray diffraction and to convert the crystal structure from cubic to wurtzite. Measured transfer characteristics showed an increase of the field effect mobility (μ(eff)) by an order of magnitude from 1.94 × 10(-4) cm(2)/(V s) to 23.4 × 10(-4) cm(2)/(V s) for pc-CdSe nanowires subjected to the CdCl(2) treatment. The CdCl(2) treatment also reduced the threshold voltage (from 20 to 5 V) and the subthreshold slope (by ~35%). Transfer characteristics for pc-CdSe NWFETs were also influenced by the channel length, L. For CdCl(2)-treated nanowires, μ(eff) was reduced by a factor of eight as L increased from 5 to 25 μm. These channel length effects are attributed to the presence of defects including breaks and constrictions within individual pc-CdSe nanowires.