Performance analysis of electrostatic and transport characteristics of underlap-engineered gate-all-around carbon nanotube (CNT) FETs for nanoelectronics circuitry applications.

A cylindrical gate-all-around (GAA) carbon nanotube field-effect transistor (CNT FET) utilizing a semiconducting zig-zag (19,0) nanotube channel is developed for sub-10-nm technology applications. The device incorporates a conformal high-k lanthanum oxide gate dielectric forming a wrap-gate architecture, enabling strong electrostatic confinement under aggressive device scaling. To regulate carrier transport and mitigate short-channel effects, underlap engineering is systematically introduced with lengths ranging from 0 to 5 nm, resulting in six device configurations (Devices A-F). Self-consistent quantum transport simulations based on the non-equilibrium Green's function (NEGF) formalism reveal a distinct trade-off between drive capability and electrostatic integrity within the device. Performance evaluation is conducted using key electrostatic and carrier transport metrics. Compared with the non-underlap configuration (Device A), the optimized 3 nm underlap device (Device D) exhibits a 50.7% reduction in off-state leakage current, a 23.7% improvement in subthreshold swing, and a 26.5% suppression in drain-induced barrier lowering, while enhancing the switching ratio by 84.5% with minimal degradation in drive current. Furthermore, linearity and harmonic distortion analysis indicates reduced higher-order components, confirming improved analog stability under RF operating conditions for advanced nanoelectronic applications.