Step-Necked Tunnel Constrictions in Si Nanowires Enable 40 K Quantum-Dot Single-Hole Transistors without High-Resolution Lithography.

Silicon single hole transistors (SHTs) are essential components for spin- and charge-based quantum computing and logics. However, fabricating ultrasmall quantum dots (QDs) or Coulomb islands bounded by a pair of ultrathin tunnel-barrier junctions remains a major technical bottleneck. Here, we show that such delicate SHT structures can be created at prescribed locations during an in-plane solid-liquid-solid (IPSLS) growth of ultrathin silicon nanowire (SiNW) channels. By directing the SiNWs to grow and jump across closely spaced double-steps, the leading catalytic droplets are stretched by interfacial forces at the sharp convex corners, to generate a pair of sub-10 nm tunnel constrictions, flanking a central QD island of ∼50 nm-wide. Quantum confinement in these step-necked constrictions was found to be strong enough to control individual hole transports through the Si-QD, as evidenced by pronounced Coulomb blockade oscillation and well-defined Coulomb diamonds persisting up to 40 K. This step-necked QD formation mechanism circumvents the use of high-resolution lithography, offering an extremely low-cost but scalable and deterministic route to batch-manufacture Si-based QD structures for SHT logics and spin qubits.