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Nature communications · 2026

Dielectric stacking-engineered scalable reconfigurable transistor platform for adaptive logic circuits.

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Zhu Pengfei, Zhang Chi, Yang Jingbo, Guo You-Wei, Huo Shida, Wu Enxiu, Wang Fei, Lin Che-Yi, Chen Jyun-Hong, Chu Hongling, Liu Zhaorui, Zhao Song, Li Jun, Li Mengjiao, Lin Yen-Fu, Zhang Jianhua

Аннотация

Although reconfigurable van der Waals devices featuring flexible logic transformation offer a promising strategy toward adaptable architectures to accommodate diverse computational demands, reliable polarity control and scalable integration remain challenging. Here, we demonstrate a reconfigurable field-effect transistor based on the scalable dielectric oxide-van der Waals quasi-floating-gate configuration, enabling nonvolatile polarity switching and multi-state programmability. Charge trapping engineering in an atomic-layer Al2O3/HfO2/Al2O3 dielectric stack achieves performance with nonvolatile conductance update (>6-bits for 1000 s), robust endurance (>3 × 105 cycles), and well-balanced electron/hole transport (current mismatch ratio ~ 1%). TCAD simulation and surface potential analysis reveal oxygen vacancies-dominated polarity switching dynamics. Using a silicon-compatible top-gate dielectric process and complementary design, diverse logic gates-including eight Boolean operations and seamless AND-OR-Invert/OR-AND-Invert transformations-are accommodated into compact reconfigurable logic-in-memory circuits. These transistors also simplify ternary content-addressable memory design, underscoring their potential for efficient logic-in-memory computing.

ИП Урсолов Владлен Сергеевич

ИНН 500118482352 · ОГРНИП 314500117700049

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