IEEE transactions on ultrasonics, ferroelectrics, and frequency control · 2025
FPGA-Accelerated CNN Reconstruction for Low-Power Sparse-Array Ultrasound Imaging.
СтатьяНазвание и аннотация: Перевод пока не подготовлен
Обработка статьи · этапы, ошибки и управление
Загрузка состояния…
Ошибки и ограничения
История · было → стало
Состояние обновляется каждые 5 секунд, пока блок открыт. Процент показывается только там, где известен объём работы. Пауза останавливает продолжение этапа; текущий запрос к источнику может завершиться.
Imenabadi Rouzbeh Molaei, Thoreson Gregory R, Brown Katherine G, Bhatia Dinesh
Аннотация
Imaging of targeted organs, such as the urinary bladder, could be transformative for preventive healthcare and early disease diagnosis when used to assess their real-time function. However, wearable and portable ultrasound (US) imaging systems often face constraints related to power consumption, form factor, cost, and signal resolution, particularly for deep tissues like the bladder. High-accuracy platforms with large channel counts can generate data streams of up to 10 GB/s, posing significant challenges in reducing computational complexity, achieving power efficiency, and maintaining wireless connectivity. Recent advancements in wearable US sensors have demonstrated potential for low-power, unobtrusive solutions but often fail to meet the accuracy and efficiency needed in clinical settings. This work presents an algorithm-centric proof of concept that reconstructs missing US channels through field-programmable gate array (FPGA)-accelerated deep learning, effectively doubling the imaging aperture while halving analog front-end requirements. We developed a lightweight U-Net convolutional neural network (L-UNET) with 222 609 parameters, specifically optimized for sparse-array RF data reconstruction. The network is deployed on a deep learning processing unit (DPU) using mixed quantization-aware training (Mixed-QAT) that selectively applies 8-bit integer precision while preserving two critical layers at 16-bit floating point (FP), achieving mean-squared error (MSE) of 1.48 $\times$ 10 compared to 1.22 $\times$ 10 for 32-bit FP. The FPGA implementation leverages a single-core accelerator, executing inference in 221 ms/frame with deterministic latency suitable for real-time reconstruction. By processing only odd-indexed physical channels and inferring even-indexed channels through the convolutional neural network (CNN), our approach maintains B-mode image quality (peak signal-to-noise ratio (PSNR) >18 dB and structural similarity index (SSIM) > 0.5) while reducing data acquisition complexity. The system achieves 0.918-W average power consumption in a 32-channel configuration, demonstrating that CNNbased sparse-array reconstruction on embedded FPGAs offers a viable path toward fully integrated US monitoring systems.